Electrical and Computer Engineering
Prof. Zhiru Zhang joined the School of Electrical and Computer Engineering at Cornell University as an assistant professor in August 2012 and was elevated to the rank of associate professor in July 2018. He is a member of the Computer Systems Laboratory.
Prof. Zhang received an M.S. and Ph.D. in Computer Science from the University of California, Los Angeles, and received a B.S. in Computer Science from Peking University. In 2006, he co-founded AutoESL Design Technologies, Inc. based on his dissertation research on high-level synthesis (HLS). AutoESL was acquired by Xilinx in 2011 and its HLS tool is now known as Vivado HLS, which is the first mainstream and most widely deployed C-based design tool for FPGAs. Prior to joining Cornell, he served as a software development manager at Xilinx, where he received the 2012 Ross Freeman Award for Technical Innovation, the highest technical award given by Xilinx.
Prof. Zhang’s research has earned several awards, among them a best paper award from the ACM Transactions on Design Automation of Electronic Systems (TODAES), a Best Short Paper Award from IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM 2018), and multiple best paper nominations (ICCAD 2009, FPGA 2017, FPGA 2018).
Prof. Zhang’s research broadly investigates new applications, optimization algorithms, and design automation tools for heterogeneous computing. recent publications focus on the topics of high-level synthesis, accelerator architectures, programming for FPGAs, and algorithm-hardware co-design for machine learning.
Digital Logic Design, Electronic Design Automation
- Y. Zhou, U. Gupta, S. Dai, R. Zhao, N. Srivastava, H. Jin, J. Featherston, Y.-H. Lai, G. Liu, G. Velasquez, W. Wang, and Z. Zhang, Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs, International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2018.
- S. Dai, G. Liu, and Z. Zhang, A Scalable Approach to Exact Resource-Constrained Scheduling Based on a Joint SDC and SAT Formulation, International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2018.
- T. Ajayi, K. Al-Hawaj, A. Amarnath, S. Dai, S. Davidson, P. Gao, G. Liu, A. Lotfi, J. Puscar, A. Rao, A. Rovinski, L. Salem, N. Sun, C. Torng, L. Vega, B. Veluri, X. Wang, S. Xie, C. Zhao, R. Zhao, C. Batten, R. Dreslinski, I. Galton, R. Gupta, P. Mercier, M. Srivastava, M. Taylor, and Z. Zhang, Celerity: An Open-Source RISC-V Tiered Accelerator Fabric, ACM/IEEE Symposium on High-Performance Chips (HOTCHIPS), Aug. 2017.
- R. Zhao, W. Song, W. Zhang, T. Xing, J.-H. Lin, M. Srivastava, R. Gupta, and Z. Zhang, Accelerating Binarized Convolutional Neural Networks with Software-Programmable FPGAs, International Symposium on Field-Programmable Gate Arrays (FPGA), Feb. 2017.
- G. Liu, M. Tan, S. Dai, R. Zhao, and Z. Zhang, Architecture and Synthesis for Area-Efficient Pipelining of Irregular Loop Nests, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Feb. 2017.
Selected Awards and Honors
- DAC Under 40 Young Innovator Award (Design Automation Conference) 2018
- Michael Tien ’72 Excellence in Teaching Award from College of Engineering 2016
- IEEE CEDA Ernest S. Kuh Early Career Award (Council on Electronic Design Automation) 2015
- DARPA Young Faculty Award (Defense Advanced Research Projects Agency) 2015
- NSF Career Award (National Science Foundation) 2015
- B.S. (Computer Science), Peking University, 2001
- M.S. (Computer Science), University of California, Los Angeles, 2003
- Ph.D. (Computer Science), University of California, Los Angeles, 2007